1. Field of the Invention
The present invention relates to a large scale integrated circuit (LSI) design system, logic correction support equipment, a logic correction support method used therefor, and a program therefor, and more specifically to a method for correcting an already synthesized logic circuit during LSI design.
2. Description of the Related Art
Conventionally, in designing an LSI, a given hardware specification is stepwise embodied in a more concrete form by a series of design processes consisting of a function design, a logic design, a circuit design, a layout design, etc. and finally the specification thus embodied is mapped into a mask pattern. In each design process, although the design is normally performed using a computer, the design is seldom done automatically only by a computer without human hands, and a system with a computer supporting manual design is employed.
In the function design among the design processes of an LSI, an operation synthesizer tool that converts an operation description expressing an operation of hardware to a description of a register transfer level (RTL) that will be an input of a logic synthesizer tool has been developed, and the use of such a tool makes it possible to drastically shorten a design time.
Moreover, in the logic design, the logic synthesizer tool for converting a description of the RTL into a logic circuit of gate level has been developed. When employing the logic synthesizer tool, the designer can set up several constraint conditions such as a chip area and a delay time. The layout design is one of the most automated design processes from its initial phase, and there has been developed an automated layout tool that, when macro cells and connection relations therebetween are inputted, arranges them on a chip and determines wiring paths among the macro cells.
In the conventional LSI design mentioned above, when, regarding a logic circuit synthesized from an RTL by logic synthesis, apart of the logic is intended to be altered, normally if the logic circuit is re-synthesized from the RTL, the whole of the circuit will be constrained to be altered although correction is only a part of the circuit. Then, the designer will inevitably correct the already synthesized logic circuit manually.
However, in the conventional LSI design, there may be a case where a logic that was erased in the LSI because of redundancy before logic correction will become non-redundant by the logic correction, as shown in FIG. 10. Since the redundant logic has already been erased in the synthesized logic circuit as shown in FIG. 11, it is therefore necessary to restore a portion that becomes non-redundant by the logic correction. In such a case, the conventional LSI design necessitates restoring this redundant logic; however, there is often the case where the existence of the redundant logic cannot be discovered and the logic correction becomes very difficult.
As a technique related to the present application, for example, Japanese Patent Laid-open Application (JP-A) No. 2005-165681 discloses a technique that addresses the problem. By this technique, a duplex circuit and a main circuit are integrated into one in the process of optimization of a circuit in LSI design. To solve this problem, the integrated circuit extracts output ports of the duplex circuit and of the main circuit from a net list, traces each extracted port down to the input side, and checks whether there is an overlap.